The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing a nanosheet containing device in which parasitic leakage current under a vertical stack of semiconductor channel nanosheets is prevented. The present application also relates to a method of forming such a semiconductor structure.
The use of non-planar semiconductor devices such as, for example, a nano sheet containing device is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions (i.e., nanosheets) having a vertical thickness that is substantially less than its width. Nanosheet containing device formation relies on the selective removal of one semiconductor material (e.g., a silicon germanium alloy) to another semiconductor material (e.g., silicon) to form suspended nanosheets for gate-all-around devices.
In current nanosheet containing devices, the functional gate structure that wraps around the bottommost semiconductor channel material nanosheet also touches the semiconductor substrate which can lead to potential leakage paths. Also, and in current nanosheet containing devices, the source/drain regions are not in close proximity to the channel of the nanosheet containing device. There is thus a need for providing nanosheet containing devices having a local isolation region under the source/drain region to prevent parasitic leakage current under the channel and with source/drain epitaxy in close proximity to the channel so as to obtain sharp source/drain junctions.